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Built-in variables and constants

Table 19 lists the built-in variables defined by armasm.

Table 19. Built-in variables

{ARCHITECTURE}

Holds the name of the selected ARM architecture.

{AREANAME}Holds the name of the current AREA.
{ARMASM_VERSION}

Holds an integer that increases with each version of armasm. The format of the version number is PVbbbb where:

P

is the major version

V

is the minor version

bbbb

is the build number.

Note

The built-in variable |ads$version| is deprecated.

{CODESIZE}

Is a synonym for {CONFIG}.

{COMMANDLINE}Holds the contents of the command line.

{CONFIG}

Has the value:

  • 64 if the assembler is assembling A64 code

  • 32 if the assembler is assembling A32 code

  • 16 if the assembler is assembling T32 code.

{CPU}

Holds the name of the selected processor. The value of {CPU} is derived from the value specified in the --cpu option on the command line.

{ENDIAN}

Has the value “big” if the assembler is in big-endian mode, or “little” if it is in little-endian mode.

{FPU}Holds the name of the selected FPU. The default in AArch32 state is "FP-ARMv8". The default in AArch64 state is "A64".
{INPUTFILE}Holds the name of the current source file.
{INTER}Has the boolean value {True} if --apcs=/inter is set. The default is {False}.
{LINENUM}Holds an integer indicating the line number in the current source file.
{LINENUMUP}When used in a macro, holds an integer indicating the line number of the current macro. The value is the same as {LINENUM} when used in a non-macro context.
{LINENUMUPPER}When used in a macro, holds an integer indicating the line number of the top macro. The value is the same as {LINENUM} when used in a non-macro context.

{OPT}

Value of the currently-set listing option. You can use the OPT directive to save the current listing option, force a change in it, or restore its original value.

{PC} or .

Address of current instruction.

{PCSTOREOFFSET}

Is the offset between the address of the STR PC,[…] or STM Rb,{…, PC} instruction and the value of PC stored out. This varies depending on the processor or architecture specified.

{VAR} or @

Current value of the storage area location counter.


Built-in variables cannot be set using the SETA, SETL, or SETS directives. They can be used in expressions or conditions, for example:

        IF {ARCHITECTURE} = "8-A"

The names of the built-in variables can be in uppercase, lowercase, or mixed. For example:

        IF {CpU} = "Generic ARM"

Note

All built-in string variables contain case-sensitive values. Relational operations on these built-in variables do not match with strings that contain an incorrect case. Use the command-line options --cpu and --fpu to determine valid values for {CPU}, {ARCHITECTURE}, and {FPU}.

Table 20 lists the built-in Boolean constants defined by armasm.

Table 20. Built-in Boolean constants

{FALSE}

Logical constant false.

{TRUE}

Logical constant true.


Table 21 lists the target processor related built-in variables that are predefined by armasm. Where the value field is empty, the symbol is a boolean value and the meaning column describes when its value is {TRUE}.

Table 21. Predefined macros
NameValueMeaning
{TARGET_ARCH_AARCH32}boolean{TRUE} when assembling for AArch32 state. {FALSE} when assembling for AArch64 state.
{TARGET_ARCH_AARCH64}boolean{TRUE} when assembling for AArch64 state. {FALSE} when assembling for AArch32 state.
{TARGET_ARCH_ARM}numThe number of the ARM base architecture of the target processor irrespective of whether the assembler is assembling for A32 or T32. The value is defined as zero when assembling for A64, and eight when assembling for A32/T32.
{TARGET_ARCH_THUMB}num

The number of the T32 base architecture of the target processor irrespective of whether the assembler is assembling for A32 or T32. The value is defined as zero when assembling for A64 and five when assembling for A32/T32.

{TARGET_FEATURE_EXTENSION_REGISTER_COUNT}num

The number of SIMD or floating-point 64-bit extension registers available.

{TARGET_FEATURE_CLZ}-

If the target processor supports the CLZ instruction.

{TARGET_FEATURE_DIVIDE}-

If the target processor supports the hardware divide instructions SDIV and UDIV.

{TARGET_FEATURE_DOUBLEWORD}-

If the target processor supports doubleword load and store instructions, for example the A32 and T32 instructions LDRD and STRD.

{TARGET_FEATURE_DSPMUL}-If the DSP-enhanced multiplier (for example the SMLAxy instruction) is available.
{TARGET_FEATURE_MULTIPLY}-

If the target processor supports long multiply instructions, for example the A32 and T32 instructions SMULL, SMLAL, UMULL, and UMLAL.

{TARGET_FEATURE_MULTIPROCESSING}-

If assembling for a target processor with Multiprocessing Extensions.

{TARGET_FEATURE_NEON}-

If the target processor has Advanced SIMD.

{TARGET_FEATURE_NEON_FP16}-

If the target processor has Advanced SIMD with half-precision floating-point operations.

{TARGET_FEATURE_NEON_FP32}-

If the target processor has Advanced SIMD with single-precision floating-point operations.

{TARGET_FEATURE_NEON_INTEGER}-

If the target processor has Advanced SIMD with integer operations.

{TARGET_FEATURE_UNALIGNED}-

If the target processor has support for unaligned accesses.

{TARGET_FPU_SOFTVFP}-If assembling with the option --fpu=softvfp.
{TARGET_FPU_SOFTVFP_VFP}-If assembling for a target processor with softvfp and floating-point hardware, for example --fpu=softvfp+fp-armv8.
{TARGET_FPU_VFP}-If assembling for a target processor with floating-point hardware, without using softvfp, for example --fpu=fp-armv8.
{TARGET_FPU_VFPV2}-If assembling for a target processor with VFPv2.
{TARGET_FPU_VFPV3}-If assembling for a target processor with VFPv3.
{TARGET_PROFILE_A}-If assembling for a Cortex™-A profile processor.
{TARGET_PROFILE_M}-

If assembling for a Cortex-M profile processor.

{TARGET_PROFILE_R}-If assembling for a Cortex-R profile processor.

See also

Reference

armasm Reference Guide:

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