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BX

Branch and exchange instruction set.

Syntax

BX{cond} Rm

where:

cond

is an optional condition code. cond is not available on all forms of this instruction.

Rm

is a register containing an address to branch to.

Operation

The BX instruction causes a branch to the address contained in Rm and exchanges the instruction set, if required:

  • The BX instruction can change the instruction set.

    BX Rm derives the target instruction set from bit[0] of Rm:

    • If bit[0] of Rm is 0, the processor changes to, or remains in, A32 state.
    • If bit[0] of Rm is 1, the processor changes to, or remains in, T32 state.

Note

There are no equivalent instructions to BX to change between AArch32 and AArch64 state. The only way to change execution state is by a change of exception level.

Instruction availability and branch ranges

The following table shows the instructions that are available in A32 and T32 state. Instructions that are not shown in this table are not available.

Table 13-7 BX instruction availability and range

Instruction A32 T32, 16-bit encoding T32, 32-bit encoding
BX Rm Available Available Use 16-bit
BX{cond} Rm Available - -

Register restrictions

You can use PC for Rm in the A32 BX instruction, but this is deprecated. You cannot use PC in other A32 instructions.

You can use PC for Rm in the T32 BX instruction. You cannot use PC in other T32 instructions.

You can use SP for Rm in the A32 BX instruction but this is deprecated in ARMv6T2 and above.

You can use SP for Rm in the T32 BX instruction, but this is deprecated.

Condition flags

The BX instruction does not change the flags.

Availability

See the preceding table for details of availability of the BX instruction in both instruction sets.

Related reference

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