Signed halving parallel subtract and add halfwords with exchange.
is an optional condition code.
is the destination register.
are the ARM registers holding the operands.
This instruction exchanges the two halfwords of the second operand, then performs a subtraction on the two top halfwords of the operands and an addition on the bottom two halfwords. It halves the results and writes them into the corresponding halfwords of the destination. This cannot cause overflow.
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
This instruction does not affect the N, Z, C, V, Q, or GE flags.
The 32-bit instruction is available in A32 and T32.
There is no 16-bit version of this instruction in T32.