SMUAD
Dual 16-bit Signed Multiply with Addition of products, and optional exchange of operand halves.
Syntax
SMUAD
{X
}{
}
{cond
},
Rd
,
Rn
Rm
where:
X
is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.
cond
is an optional condition code.
Rd
is the destination register.
Rn, Rm
are the registers holding the operands.
Operation
SMUAD
multiplies the bottom halfword
of
with the bottom halfword of Rn
,
and the top halfword of Rm
with
the top halfword of Rn
. It then
adds the products and stores the sum to Rm
.Rd
Register restrictions
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
Q flag
The SMUAD
instruction sets the
Q flag if the addition overflows.
Availability
The 32-bit instruction is available in A32 and T32.
There is no 16-bit version of this instruction in T32.
Examples
SMUAD r2, r3, r2