UHSUB8
Unsigned halving parallel byte-wise subtraction.
Syntax
UHSUB8{condRdRnRm
where:
condis an optional condition code.
Rdis the destination register.
Rm, Rnare the ARM registers holding the operands.
Operation
This instruction subtracts each byte of the second operand from the corresponding byte of the first operand, halves the results, and writes the results into the corresponding bytes of the destination. This cannot cause overflow.
Register restrictions
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
Condition flags
This instruction does not affect the N, Z, C, V, Q, or GE flags.
Availability
The 32-bit instruction is available in A32 and T32.
There is no 16-bit version of this instruction in T32.