VMOV (between two ARM registers and one or two extension registers)
Transfer contents between two ARM registers and either one 64-bit register or two consecutive 32-bit registers.
Syntax
VMOV
{
}
cond
, Dm
,
Rd
Rn
VMOV
{
}
cond
, Rd
,
Rn
Dm
VMOV
{
}
cond
, Sm
,
Sm1
,
Rd
Rn
VMOV
{
}
cond
, Rd
,
Rn
,
Sm
Sm1
where:
cond
is an optional condition code.
Dm
is a 64-bit extension register.
Sm
is a VFP 32-bit register.
Sm1
is the next consecutive VFP 32-bit register after
.Sm
Rd
,Rn
are the ARM registers.
R
andd
R
must not be PC.n
Operation
VMOV
transfers
the contents of Dm
, Rd
, Rn
into the low
half of Rd
, and the contents of Dm
into the
high half of Rn
.Dm
VMOV
transfers
the contents of the low half of Rd
, Rn
, Dm
into Dm
,
and the contents of the high half of Rd
into Dm
.Rn
VMOV
transfers
the contents of Rd
, Rn
, Sm
, Sm1
Sm
into Rd
,
and the contents of
into Sm1
.Rn
VMOV
transfers
the contents of Sm
, Sm1
, Rd
, Rn
Rd
into Sm
,
and the contents of
into Rn
.Sm1
Architectures
The instructions are available in VFPv2 and above.