13.12 ADRL pseudo-instruction
Load a PC-relative or register-relative address into a register.
is an optional condition code.
is the register to load.
is a PC-relative or register-relative expression.
ADRL always assembles to two 32-bitinstructions. Even if the address can be reached in a single instruction,a second, redundant instruction is produced.
If the assembler cannot construct the address in two instructions,it generates an error message and the assembly fails. You can usethe
LDR pseudo-instruction for loadinga wider range of addresses.
ADRL is similar to the
ADR instruction, except
ADRL can load a wider range of addresses because it generates two data processing instructions.
ADRL produces position-independentcode, because the address is PC-relative or register-relative.
label is PC-relative,it must evaluate to an address in the same assembler area as the
If you use
ADRL to generate a target for a
BLX instruction, it is your responsibility to set the T32 bit (bit 0) of the address if the target contains T32 instructions.
Architectures and range
The available range depends on the instruction set in use:
The range of the instruction is any value that can be generated by two
SUBinstructions. That is, any value that can be produced by the addition of two values, each of which is 8 bits rotated right by any even number of bits within a 32-bit word.
- T32, 32-bit encoding
±1MB bytes to a byte, halfword, or word-aligned address.
- T32, 16-bit encoding
ADRLis not available.
The given range is relative to a point four bytes (in T32 code) or two words (in A32 code) after the address of the current instruction.
NoteWhen assembling T32 instructions,
ADRLis only available in ARMv6T2 and later.