Instruction Synchronization Barrier.
is an optional condition code.
is permitted only in T32 code. This is an unconditional instruction in A32.
is an optional limitation on the operation of thehint. The permitted value is:
DMBoperation. This is the default and can be omitted.
Instruction Synchronization Barrier flushes the pipeline inthe processor, so that all instructions following the
ISB arefetched from cache or memory, after the instruction has been completed. Itensures that the effects of context altering operations, such aschanging the ASID, or completed TLB maintenance operations, or branchpredictor maintenance operations, in addition to all changes tothe CP15 registers, executed before the
ISB instructionare visible to the instructions fetched after the
In addition, the
ISB instructionensures that any branches that appear in program order after it arealways written into the branch prediction logic with the contextthat is visible after the
ISB instruction.This is required to ensure correct execution of the instructionstream.
NoteWhen the target architecture is ARMv7-M, you cannot use an
ISBinstructionin an IT block, unless it is the last instruction in the block.
This 32-bit instructions are available in A32 and T32.
There is no 16-bit version of this instruction in T32.