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13.44 LDAEX

Load-Acquire Register Exclusive.


This instruction is supported only in ARMv8.


LDAEX{cond} Rt, [Rn]

LDAEXB{cond} Rt, [Rn]

LDAEXH{cond} Rt, [Rn]

LDAEXD{cond} Rt, Rt2, [Rn]


is an optional condition code.
is the register to load.
is the second register for doubleword loads.
is the register on which the memory address is based.


LDAEX loads data from memory.

  • If the physical address has the SharedTLB attribute, LDAEX tags the physicaladdress as exclusive access for the current processor, and clearsany exclusive access tag for this processor for any other physicaladdress.
  • Otherwise, it tags the fact that the executing processorhas an outstanding tagged physical address.
  • If any loads or stores appear after LDAEX inprogram order, then all observers are guaranteed to observe the LDAEX beforeobserving the loads and stores. Loads and stores appearing before LDAEX areunaffected.


The PC must not be used for any of Rt, Rt2, or Rn.

For A32 instructions:

  • SP can be used but use of SP for any of Rt, or Rt2 is deprecated.
  • For LDAEXD, Rt must be an even numbered register, and not LR.
  • Rt2 must be R(t+1).

For T32 instructions:

  • SP can be used for Rn, but must not be used for any of Rt, or Rt2.
  • For LDAEXD, Rt and Rt2 mustnot be the same register.


Use LDAEX and STLEX toimplement interprocess communication in multiple-processor and shared-memorysystems.

For reasons of performance, keep the number of instructionsbetween corresponding LDAEX and STLEX instructionsto a minimum.


The address used in a STLEX instructionmust be the same as the address in the most recently executed LDAEX instruction.


These 32-bit instructions are available in A32 and T32.

There are no 16-bit versions of these instructions.