13.65 MRS (PSR to general-purpose register)
Move the contents of a PSR to a general-purpose register.
is an optional condition code.
is the destination register.
is one of:
on any processor, in any mode.
deprecated synonym for APSR and for use in Debugstate, on any processor except ARMv7-M and ARMv6-M.
on any processor except ARMv7-M and ARMv6-M, inprivileged software execution only.
on ARMv7-M and ARMv6-M processors only.
can be any of:
MRS in combination with
MSR aspart of a read-modify-write sequence for updating a PSR, for exampleto change processor mode, or to clear the Q flag.
In process swap code, the programmersâ€™ model state of theprocess being swapped out must be saved, including relevant PSRcontents. Similarly, the state of the process being swapped in mustalso be restored. These operations make use of
MSR instruction sequences.
You must not attempt to access the SPSR when the processoris in User or System mode. This is your responsibility. The assemblercannot warn you about this, because it has no information aboutthe processor mode at execution time.
ARM deprecates reading the CPSR endianness bit (E) with an
The CPSR execution state bits, other than the E bit, can onlybe read when the processor is in Debug state, halting debug-mode.Otherwise, the execution state bits in the CPSR read as zero.
The condition flags can be read in any mode on any processor. Use APSR if you are only interested in accessing the condition flags in User mode.
You cannot use PC for
R in A32 instructions. You can use SP for
R in A32 instructions but this is deprecated.
You cannot use PC or SP for
R in T32 instructions.
This instruction does not change the flags.
This instruction is available in A32 and T32.
There is no 16-bit version of this instruction in T32.