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13.81 QADD16

Signed saturating parallel halfword-wise addition.

Syntax

QADD16{cond} {Rd}, Rn, Rm

where:

cond

is an optional condition code.

Rd

is the destination register.

Rm, Rn

are the ARM registers holding the operands.

Operation

This instruction performs two signed integer additions onthe corresponding halfwords of the operands and writes the resultsinto the corresponding halfwords of the destination. It saturates theresults to the signed range –215x ≤215 –1. The Q flag is not affected evenif this operation saturates.

Register restrictions

You cannot use PC for any operand.

You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.

Condition flags

This instruction does not affect the N, Z, C, V, Q, or GEflags.

Availability

The 32-bit instruction is available in A32 and T32.

There is no 16-bit version of this instruction in T32.

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