Signed saturating parallel halfword-wise subtraction.
is an optional condition code.
is the destination register.
are the ARM registers holding the operands.
This instruction subtracts each halfword of the second operandfrom the corresponding halfword of the first operand and writesthe results into the corresponding halfwords of the destination.It saturates the results to the signed range –215 ≤
x ≤215 –1. The Q flag is not affected evenif this operation saturates.
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
This instruction does not affect the N, Z, C, V, Q, or GEflags.
The 32-bit instruction is available in A32 and T32.
There is no 16-bit version of this instruction in T32.