Signed halving parallel byte-wise addition.
is an optional condition code.
is the destination register.
are the ARM registers holding the operands.
This instruction performs four signed integer additions onthe corresponding bytes of the operands, halves the results, andwrites the results into the corresponding bytes of the destination.This cannot cause overflow.
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
This instruction does not affect the N, Z, C, V, Q, or GEflags.
The 32-bit instruction is available in A32 and T32.
There is no 16-bit version of this instruction in T32.