You copied the Doc URL to your clipboard.

13.114 SHSUB16

Signed halving parallel halfword-wise subtraction.


SHSUB16{cond} {Rd}, Rn, Rm



is an optional condition code.


is the destination register.

Rm, Rn

are the ARM registers holding the operands.


This instruction subtracts each halfword of the second operandfrom the corresponding halfword of the first operand, halves theresults, and writes the results into the corresponding halfwords ofthe destination. This cannot cause overflow.

Register restrictions

You cannot use PC for any operand.

You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.

Condition flags

This instruction does not affect the N, Z, C, V, Q, or GEflags.


The 32-bit instruction is available in A32 and T32.

There is no 16-bit version of this instruction in T32.

Related reference

Was this page helpful? Yes No