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13.139 STL

Store-Release Register.


This instruction is supported only in ARMv8.


STL{cond} Rt, [Rn]

STLB{cond} Rt, [Rn]

STLH{cond} Rt, [Rn]


is an optional condition code.
is the register to store.
is the register on which the memory address is based.


STL stores data to memory. If any loads or stores appearbefore a store-release in program order, then all observers are guaranteed toobserve the loads and stores before observing the store-release. Loads and storesappearing after a store-release are unaffected.

If a store-release follows a load-acquire, each observer is guaranteed to observethem in program order.

There is no requirement that a store-release be paired with aload-acquire.

All store-release operations are multi-copy atomic, meaning that in a multiprocessingsystem, if one observer observes a write to memory because of a store-releaseoperation, then all observers observe it. Also, all observers observe all suchwrites to the same location in the same order.


The address specified must be naturally aligned, or an alignment fault isgenerated.

The PC must not be used for Rt orRn.


This 32-bit instruction is available in A32 and T32.

There is no 16-bit version of this instruction.

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