You copied the Doc URL to your clipboard.

13.147 SUBS pc, lr

Exception return, without popping anything from the stack.

Syntax

SUBS{cond} pc, lr, #imm ; A32 and T32 code

MOVS{cond} pc, lr ; A32 and T32 code

op1S{cond} pc, Rn, #imm ; A32 code only and is deprecated

op1S{cond} pc, Rn, Rm {, shift} ; A32 code only and is deprecated

op2S{cond} pc, #imm ; A32 code only and is deprecated

op2S{cond} pc, Rm {, shift} ; A32 code only and is deprecated

where:

op1

is one of ADC, ADD, AND, BIC, EOR, ORN, ORR, RSB, RSC, SBC,and SUB.

op2

is one of MOV and MVN.

cond

is an optional condition code.

imm

is an immediate value. In T32 code, it is limited to the range 0-255. In A32 code, it is a flexible second operand.

Rn

is the first operand register. ARM deprecates theuse of any register except LR.

Rm

is the optionally shifted second or only operandregister.

shift

is an optional condition code.

Usage

SUBS pc, lr, #imm subtractsa value from the link register and loads the PC with the result,then copies the SPSR to the CPSR.

You can use SUBS pc, lr, #imm toreturn from an exception if there is no return state on the stack. Thevalue of #imm depends on the exceptionto return from.

Notes

SUBS pc, lr, #imm writesan address to the PC. The alignment of this address must be correct forthe instruction set in use after the exception return:

  • For a return to A32, the address written to the PC must be word-aligned.
  • For a return to T32, the address written to the PC must be halfword-aligned.
  • For a return to Jazelle, there are no alignment restrictions on the address written to the PC.

No special precautions are required in software to followthese rules, if you use the instruction to return after a validexception entry mechanism.

In T32, only SUBS{cond} pc, lr, #imm is a valid instruction. MOVS pc, lr is a synonym of SUBS pc, lr, #0. Other instructions are undefined.

In A32, only SUBS{cond} pc, lr, #imm and MOVS{cond} pc, lr are valid instructions. Other instructions are deprecated.

Do not use these instructions in User mode or System mode. The assembler cannot warn you about this.

Availability

This 32-bit instruction is available in A32 and T32.

There is no 16-bit version of this instruction in T32.

Was this page helpful? Yes No