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13.148 SVC

SuperVisor Call.


SVC{cond} #imm



is an optional condition code.


is an expression evaluating to an integer in therange:

  • 0 to 224-1 (a 24-bit value) in an A32 instruction.

  • 0-255 (an 8-bit value) in a T32 instruction.


The SVC instruction causes an exception.This means that the processor mode changes to Supervisor, the CPSRis saved to the Supervisor mode SPSR, and execution branches tothe SVC vector.

imm is ignored by theprocessor. However, it can be retrieved by the exception handlerto determine what service is being requested.


SVC was called SWI in earlier versions of the A32 assembly language. SWI instructions disassemble to SVC, with a comment to say that this was formerly SWI.

Condition flags

This instruction does not change the flags.


This instruction is available in A32 and 16-bit T32 and in the ARMv7 architectures.

There is no 32-bit version of this instruction in T32.

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