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18.3 FADD (scalar)

Floating-point add.

Syntax

FADD Sd, Sn, Sm ; Single-precision

FADD Dd, Dn, Dm ; Double-precision

Where:

Sd

Is the 32-bit name of the SIMD and FP destination register.

Sn

Is the 32-bit name of the first SIMD and FP source register.

Sm

Is the 32-bit name of the second SIMD and FP source register.

Dd

Is the 64-bit name of the SIMD and FP destination register.

Dn

Is the 64-bit name of the first SIMD and FP source register.

Dm

Is the 64-bit name of the second SIMD and FP source register.

Operation

Vd = Vn + Vm, where V is either D or S.

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