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18.23 FMADD

Floating-point fused multiply-add.

Syntax

FMADD Sd, Sn, Sm, Sa ; Single-precision

FMADD Dd, Dn, Dm, Da ; Double-precision

Where:

Sd

Is the 32-bit name of the SIMD and FP destination register.

Sn

Is the 32-bit name of the first SIMD and FP source register holding the multiplicand.

Sm

Is the 32-bit name of the second SIMD and FP source register holding the multiplier.

Sa

Is the 32-bit name of the third SIMD and FP source register holding the addend.

Dd

Is the 64-bit name of the SIMD and FP destination register.

Dn

Is the 64-bit name of the first SIMD and FP source register holding the multiplicand.

Dm

Is the 64-bit name of the second SIMD and FP source register holding the multiplier.

Da

Is the 64-bit name of the third SIMD and FP source register holding the addend.

Operation

Vd = Va + Vn*Vm, where V is either D or S.

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