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20.50 FCVTN, FCVTN2 (vector)

Floating-point convert to lower precision narrow.

Syntax

FCVTN{2} Vd.Tb, Vn.Ta

Where:

2

Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements. See Q in the Usage table.

Vd

Is the name of the SIMD and FP destination register.

Tb

Is an arrangement specifier, and can be one of the values shown in Usage.

Vn

Is the name of the SIMD and FP source register.

Ta

Is an arrangement specifier, and can be either 4S or 2D.

Usage

The following table shows the valid specifier combinations:

Table 20-8 FCVTN, FCVTN2 (Vector) specifier combinations

QTbTa
-4H4S
28H4S
-2S2D
24S2D
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