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20.56 FCVTZS (vector, fixed-point)

Floating-point convert to signed fixed-point, rounding toward zero.

Syntax

FCVTZS Vd.T, Vn.T, #fbits

Where:

Vd

Is the name of the SIMD and FP destination register.

T

Is an arrangement specifier, and can be one of the values shown in Usage.

Vn

Is the name of the SIMD and FP source register.

fbits

Is the number of fractional bits, in the range 1 to the element width.

Usage

The following table shows the valid specifier combinations:

Table 20-10 FCVTZS (Vector) specifier combinations

Tfbits
2S1 to 32
4S1 to 32
2D1 to 64
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