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20.150 SHLL, SHLL2 (vector)

Shift left long (by element size).

Syntax

SHLL{2} Vd.Ta, Vn.Tb, #shift

Where:

2

Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements. See Q in the Usage table.

Vd

Is the name of the SIMD and FP destination register.

Ta

Is an arrangement specifier, and can be one of the values shown in Usage.

Vn

Is the name of the SIMD and FP source register.

Tb

Is an arrangement specifier, and can be one of the values shown in Usage.

shift

Is the left shift amount, which must be equal to the source element width in bits, and can be one of the values shown in Usage.

Usage

The following table shows the valid specifier combinations:

Table 20-44 SHLL, SHLL2 (Vector) specifier combinations

QTaTbshift
-8H8B8
28H16B8
-4S4H16
24S8H16
-2D2S32
22D4S32
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