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20.265 UXTL, UXTL2 (vector)

Unsigned extend long.

This instruction is an alias of USHLL, USHLL2.

Syntax

UXTL{2} Vd.Ta, Vn.Tb

Equivalent to USHLL{2} Vd.Ta, Vn.Tb, #0.

Where:

2

Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements. See Q in the Usage table.

Vd

Is the name of the SIMD and FP destination register.

Ta

Is an arrangement specifier, and can be one of the values shown in Usage.

Vn

Is the name of the SIMD and FP source register.

Tb

Is an arrangement specifier, and can be one of the values shown in Usage.

Usage

The following table shows the valid specifier combinations:

Table 20-115 UXTL, UXTL2 (Vector) specifier combinations

QTaTb
-8H8B
28H16B
-4S4H
24S8H
-2D2S
22D4S
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