VLDR pseudo-instruction loads a constant value into every element of a 64-bit Advanced SIMD vector.
NoteThis description is for the
- is an optional condition code.
must be one of
- must be one of 8, 16, 32, or 64.
- is the extension register to be loaded.
- is an immediate value of the appropriate type for
If an instruction (for example,
VMOV)is available that can generate the constant directly into the register,the assembler uses it. Otherwise, it generates a doubleword literalpool entry containing the constant and loads the constant usinga