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14.63 VMOV (between an ARM register and an Advanced SIMD scalar)

Transfer contents between an ARM register and an Advanced SIMD scalar.

Syntax

VMOV{cond}{.size} Dn[x], Rd

VMOV{cond}{.datatype} Rd, Dn[x]

where:

cond

is an optional condition code.

size

the data size. Can be 8, 16, or 32. If omitted, size is 32.

datatype

the data type. Can be U8, S8, U16, S16, or 32. If omitted, datatype is 32.

Dn[x]

is the Advanced SIMD scalar.

Rd

is the ARM register. Rd mustnot be PC.

Operation

VMOV Dn[x], Rd transfersthe contents of the least significant byte, halfword, or word of Rd into Dn[x].

VMOV Rd, Dn[x] transfersthe contents of Dn[x] into theleast significant byte, halfword, or word of Rd.The remaining bits of Rd areeither zero or sign extended.

Related reference

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