Pseudo-instruction that generates an immediate value and places it in every element of an Advanced SIMD vector, without loading a value from a literal pool.
must be one of:
is an optional condition code.
- is the extension register to be loaded.
- is an immediate value of the appropriate type for
VMOV2 can generate any 16-bit immediate value, and a restricted range of 32-bit and 64-bit immediate values.
VMOV2 is a pseudo-instruction that always assembles to exactly two instructions. It typically assembles to a
VMVN instruction, followed by a