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14.123 VSTn (single n-element structure to one lane)

Vector Store single n-element structure to one lane.

Syntax

VSTn{cond}.datatypelist,[Rn{@align}]{!}

VSTn{cond}.datatypelist,[Rn{@align}],Rm

where:

n

must be one of 1, 2, 3, or 4.

cond

is an optional condition code.

datatype

see the following table.

list

is the list of Advanced SIMD registers enclosed in braces, { and }. See the following table for options.

Rn

is the ARM register containing the base address. Rn cannotbe PC.

align

specifies an optional alignment. See the following table for options.

!

if ! is present, Rn isupdated to (Rn + the number of bytestransferred by the instruction). The update occurs after all thestores have taken place.

Rm

is an ARM register containing an offset from thebase address. If Rm is present,the instruction updates Rn to (Rn + Rm) after usingthe address to access memory. Rm cannotbe SP or PC.

Operation

VSTn stores one n-element structure into memory from one or more Advanced SIMD registers.

Table 14-26 Permitted combinations of parameters for VSTn (single n-element structure to onelane)

ndatatypelist aalignbalignment
1 8{Dd[x]}-Standard only
 16{Dd[x]}@162-byte
 32{Dd[x]}@324-byte
28{Dd[x], D(d+1)[x]}@162-byte
 16{Dd[x], D(d+1)[x]}@324-byte
  {Dd[x], D(d+2)[x]}@324-byte
 32{Dd[x], D(d+1)[x]}@648-byte
  {Dd[x], D(d+2)[x]}@648-byte
38{Dd[x], D(d+1)[x], D(d+2)[x]}-Standard only
 16 or 32{Dd[x], D(d+1)[x], D(d+2)[x]}-Standard only
  {Dd[x], D(d+2)[x], D(d+4)[x]}-Standard only
48{Dd[x], D(d+1)[x], D(d+2)[x], D(d+3)[x]}@324-byte
 16{Dd[x], D(d+1)[x], D(d+2)[x], D(d+3)[x]}@648-byte
  {Dd[x], D(d+2)[x], D(d+4)[x], D(d+6)[x]}@648-byte
 32{Dd[x], D(d+1)[x], D(d+2)[x], D(d+3)[x]}@64 or @1288-byte or 16-byte
  {Dd[x], D(d+2)[x], D(d+4)[x], D(d+6)[x]}@64 or @1288-byte or 16-byte

Related reference

a 

Every register in the list must be in the range D0-D31.

b 

align can be omitted. In this case, standard alignment rulesapply.

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