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14.132 VTST

Vector Test bits.

Syntax

VTST{cond}.size {Qd}, Qn, Qm

VTST{cond}.size {Dd}, Dn, Dm

where:

cond

is an optional condition code.

size

must be one of 8, 16,or 32.

Qd, Qn, Qm

specifies the destination register, the first operandregister, and the second operand register, for a quadword operation.

Dd, Dn, Dm

specifies the destination register, the first operandregister, and the second operand register, for a doubleword operation.

Operation

VTST takes each element in a vector, and bitwise logical ANDs them with the corresponding element of a second vector. If the result is not zero, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.

Related reference