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15.11 VDIV

Floating-point divide.


VDIV{cond}.F32 {Sd}, Sn, Sm

VDIV{cond}.F64 {Dd}, Dn, Dm



is an optional condition code.

Sd, Sn, Sm

are the single-precision registers for the resultand operands.

Dd, Dn, Dm

are the double-precision registers for the resultand operands.


The VDIV instruction divides thevalue in the first operand register by the value in the second operandregister, and places the result in the destination register.

Floating-point exceptions

VDIV operations can produce Divisionby Zero, Invalid Operation, Overflow, Underflow, or Inexact exceptions.

Related reference

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