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15.15 VLDR (post-increment and pre-decrement, floating-point)

Pseudo-instruction that loads extension registers, with post-increment and pre-decrement forms.


There are also VLDR and VSTR instructionswithout post-increment and pre-decrement.


VLDR{cond}{.size} Fd, [Rn], #offset ; post-increment

VLDR{cond}{.size} Fd, [Rn, #-offset]! ; pre-decrement



is an optional condition code.


is an optional data size specifier. Must be 32 if Fd isan S register, or 64 if Fd isa D register.


is the extension register to load. It can be either a double precision (Dd) or a single precision (Sd) register.


is the ARM register holding the base address forthe transfer.


is a numeric expression that must evaluate to anumeric value at assembly time. The value must be 4 if Fd isan S register, or 8 if Fd isa D register.


The post-increment instruction increments the base addressin the register by the offset value, after the transfer. The pre-decrementinstruction decrements the base address in the register by the offsetvalue, and then performs the transfer using the new address in theregister. This pseudo-instruction assembles to a VLDM instruction.

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