You copied the Doc URL to your clipboard.

15.18 VMLA (floating-point)

Floating-point multiply accumulate.


VMLA{cond}.F32 Sd, Sn, Sm

VMLA{cond}.F64 Dd, Dn, Dm



is an optional condition code.

Sd, Sn, Sm

are the single-precision registers for the resultand operands.

Dd, Dn, Dm

are the double-precision registers for the resultand operands.


The VMLA instruction multipliesthe values in the operand registers, adds the value in the destinationregister, and places the final result in the destination register.

Floating-point exceptions

This instruction can produce Invalid Operation, Overflow,Underflow, Inexact, or Input Denormal exceptions.

Related reference

Was this page helpful? Yes No