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15.19 VMLS (floating-point)

Floating-point multiply subtract.


VMLS{cond}.F32 Sd, Sn, Sm

VMLS{cond}.F64 Dd, Dn, Dm



is an optional condition code.

Sd, Sn, Sm

are the single-precision registers for the resultand operands.

Dd, Dn, Dm

are the double-precision registers for the resultand operands.


The VMLS instruction multipliesthe values in the operand registers, subtracts the result from the valuein the destination register, and places the final result in thedestination register.

Floating-point exceptions

This instruction can produce Invalid Operation, Overflow,Underflow, Inexact, or Input Denormal exceptions.

Related reference

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