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15.26 VMUL (floating-point)

Floating-point multiply.


VMUL{cond}.F32 {Sd,} Sn, Sm

VMUL{cond}.F64 {Dd,} Dn, Dm



is an optional condition code.

Sd, Sn, Sm

are the single-precision registers for the resultand operands.

Dd, Dn, Dm

are the double-precision registers for the resultand operands.


The VMUL operation multiplies thevalues in the operand registers and places the result in the destinationregister.

Floating-point exceptions

This instruction can produce Invalid Operation, Overflow,Underflow, Inexact, or Input Denormal exceptions.

Related reference

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