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15.28 VNMLA (floating-point)

Floating-point multiply accumulate with negation.


VNMLA{cond}.F32 Sd, Sn, Sm

VNMLA{cond}.F64 Dd, Dn, Dm



is an optional condition code.

Sd, Sn, Sm

are the single-precision registers for the resultand operands.

Dd, Dn, Dm

are the double-precision registers for the resultand operands.


The VNMLA instruction multipliesthe values in the operand registers, adds the value to the destinationregister, and places the negated final result in the destinationregister.

Floating-point exceptions

This instruction can produce Invalid Operation, Overflow,Underflow, Inexact, or Input Denormal exceptions.

Related reference

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