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Floating-pointhardware

There are several floating-point architecture versions and variants.

The floating-point hardware, together with associated supportcode, provides single-precision and double-precision floating-pointarithmetic, as defined by IEEE Std. 754‑2008 IEEE Standardfor Floating-Point Arithmetic. This document is referredto as the IEEE 754 standard.

The floating-point hardware uses a register bank that is distinctfrom the ARM core register bank.

Note

The floating-point register bank is shared with the SIMD registerbank.

In AArch32 state, floating-point support is largely unchangedfrom VFPv4, apart from the addition of a few instructions for compliancewith the IEEE 754 standard.

The floating-point architecture in AArch64 state is also basedon VFPv4. The main differences are the following:

  • In AArch64 state, the numberof 128-bit SIMD and floating-point registers increases from sixteento thirty-two.
  • Single-precision registers are no longer packedinto double-precision registers, so register Sx isDx[31:0].
  • The presence of floating-point hardware is mandated,so software floating-point linkage is not supported.
  • Earlier versions of the floating-point architecture,for instance VFPv2, VFPv3, and VFPv4, are not supported in AArch64state.
  • VFP vector mode is not supported in either AArch32or AArch64 state. Use Advanced SIMD instructions for vector floating-point.
  • Some new instructions have been added, including:

    • Direct conversion between half-precision and double-precision.

    • Load and store pair, replacing load and store multiple.
    • Fused multiply-add and multiply-subtract.
    • Instructions for IEEE 754-2008 compatibility.
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