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A64 data transfer instructions in alphabetical order

A summary of the A64 data transfer instructions and pseudo-instructions that are supported.

Table 17-1 Summary of A64 data transfer instructions

Mnemonic Brief description See
LDAR Load-Acquire Register 17.3 LDAR
LDARB Load-Acquire Register Byte 17.4 LDARB
LDARH Load-Acquire Register Halfword 17.5 LDARH
LDAXP Load-Acquire Exclusive Pair of Registers 17.6 LDAXP
LDAXR Load-Acquire Exclusive Register 17.7 LDAXR
LDAXRB Load-Acquire Exclusive Register Byte 17.8 LDAXRB
LDAXRH Load-Acquire Exclusive Register Halfword 17.9 LDAXRH
LDNP (SIMD and FP) Load pair of SIMD and FP registers, with non-temporal hint 17.10 LDNP (SIMD and FP)
LDNP Load Pair of Registers, with non-temporal hint 17.11 LDNP
LDP (SIMD and FP) Load pair of SIMD and FP registers 17.12 LDP (SIMD and FP)
LDP Load Pair of Registers 17.13 LDP
LDPSW Load Pair of Registers Signed Word 17.14 LDPSW
LDR (immediate, SIMD and FP) Load SIMD and FP register (immediate offset) 17.15 LDR (immediate, SIMD and FP)
LDR (immediate) Load Register (immediate) 17.16 LDR (immediate)
LDR (literal, SIMD and FP) Load SIMD and FP register (PC-relative literal) 17.17 LDR (literal, SIMD and FP)
LDR (literal) Load Register (literal) 17.18 LDR (literal)
LDR pseudo-instruction Load a register with either a 32-bit or 64-bit immediate value or any address 17.19 LDR pseudo-instruction
LDR (register, SIMD and FP) Load SIMD and FP register (register offset) 17.20 LDR (register, SIMD and FP)
LDR (register) Load Register (register) 17.21 LDR (register)
LDRB (immediate) Load Register Byte (immediate) 17.22 LDRB (immediate)
LDRB (register) Load Register Byte (register) 17.23 LDRB (register)
LDRH (immediate) Load Register Halfword (immediate) 17.24 LDRH (immediate)
LDRH (register) Load Register Halfword (register) 17.25 LDRH (register)
LDRSB (immediate) Load Register Signed Byte (immediate) 17.26 LDRSB (immediate)
LDRSB (register) Load Register Signed Byte (register) 17.27 LDRSB (register)
LDRSH (immediate) Load Register Signed Halfword (immediate) 17.28 LDRSH (immediate)
LDRSH (register) Load Register Signed Halfword (register) 17.29 LDRSH (register)
LDRSW (immediate) Load Register Signed Word (immediate) 17.30 LDRSW (immediate)
LDRSW (literal) Load Register Signed Word (literal) 17.31 LDRSW (literal)
LDRSW (register) Load Register Signed Word (register) 17.32 LDRSW (register)
LDTR Load Register (unprivileged) 17.33 LDTR
LDTRB Load Register Byte (unprivileged) 17.34 LDTRB
LDTRH Load Register Halfword (unprivileged) 17.35 LDTRH
LDTRSB Load Register Signed Byte (unprivileged) 17.36 LDTRSB
LDTRSH Load Register Signed Halfword (unprivileged) 17.37 LDTRSH
LDTRSW Load Register Signed Word (unprivileged) 17.38 LDTRSW
LDUR (SIMD and FP) Load SIMD and FP register (unscaled offset) 17.39 LDUR (SIMD and FP)
LDUR Load Register (unscaled) 17.40 LDUR
LDURB Load Register Byte (unscaled) 17.41 LDURB
LDURH Load Register Halfword (unscaled) 17.42 LDURH
LDURSB Load Register Signed Byte (unscaled) 17.43 LDURSB
LDURSH Load Register Signed Halfword (unscaled) 17.44 LDURSH
LDURSW Load Register Signed Word (unscaled) 17.45 LDURSW
LDXP Load Exclusive Pair of Registers 17.46 LDXP
LDXR Load Exclusive Register 17.47 LDXR
LDXRB Load Exclusive Register Byte 17.48 LDXRB
LDXRH Load Exclusive Register Halfword 17.49 LDXRH
PRFM (immediate) Prefetch memory (immediate offset) 17.50 PRFM (immediate)
PRFM (literal) Prefetch memory (PC-relative offset) 17.51 PRFM (literal)
PRFM (register) Prefetch memory (register offset) 17.52 PRFM (register)
PRFUM Prefetch memory (unscaled offset) 17.53 PRFUM
STLR Store-Release Register 17.54 STLR
STLRB Store-Release Register Byte 17.55 STLRB
STLRH Store-Release Register Halfword 17.56 STLRH
STLXP Store-Release Exclusive Pair Of Registers 17.57 STLXP
STLXR Store-Release Exclusive Register 17.58 STLXR
STLXRB Store-Release Exclusive Register Byte 17.59 STLXRB
STLXRH Store-Release Exclusive Register Halfword 17.60 STLXRH
STNP (SIMD and FP) Store pair of SIMD and FP registers, with non-temporal hint 17.61 STNP (SIMD and FP)
STNP Store Pair of Registers, with non-temporal hint 17.62 STNP
STP (SIMD and FP) Store pair of SIMD and FP registers 17.63 STP (SIMD and FP)
STP Store Pair of Registers 17.64 STP
STR (immediate, SIMD and FP) Store SIMD and FP register (immediate offset) 17.65 STR (immediate, SIMD and FP)
STR (immediate) Store Register (immediate) 17.66 STR (immediate)
STR (register, SIMD and FP) Store SIMD and FP register (register offset) 17.67 STR (register, SIMD and FP)
STR (register) Store Register (register) 17.68 STR (register)
STRB (immediate) Store Register Byte (immediate) 17.69 STRB (immediate)
STRB (register) Store Register Byte (register) 17.70 STRB (register)
STRH (immediate) Store Register Halfword (immediate) 17.71 STRH (immediate)
STRH (register) Store Register Halfword (register) 17.72 STRH (register)
STTR Store Register (unprivileged) 17.73 STTR
STTRB Store Register Byte (unprivileged) 17.74 STTRB
STTRH Store Register Halfword (unprivileged) 17.75 STTRH
STUR (SIMD and FP) Store SIMD and FP register (unscaled offset) 17.76 STUR (SIMD and FP)
STUR Store Register (unscaled) 17.77 STUR
STURB Store Register Byte (unscaled) 17.78 STURB
STURH Store Register Halfword (unscaled) 17.79 STURH
STXP Store Exclusive Pair Of Registers 17.80 STXP
STXR Store Exclusive Register 17.81 STXR
STXRB Store Exclusive Register Byte 17.82 STXRB
STXRH Store Exclusive Register Halfword 17.83 STXRH