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A64 general instructions in alphabetical order

A summary of the A64 general instructions and pseudo-instructions that are supported.

Table 16-1 Summary of A64 general instructions

Mnemonic Brief description See
ADC Add with Carry 16.3 ADC
ADCS Add with Carry, setting flags 16.4 ADCS
ADD (extended register) Add (extended register) 16.5 ADD (extended register)
ADD (immediate) Add (immediate) 16.6 ADD (immediate)
ADD (shifted register) Add (shifted register) 16.7 ADD (shifted register)
ADDS (extended register) Add (extended register), setting flags 16.8 ADDS (extended register)
ADDS (immediate) Add (immediate), setting flags 16.9 ADDS (immediate)
ADDS (shifted register) Add (shifted register), setting flags 16.10 ADDS (shifted register)
ADR Form PC-relative address 16.11 ADR
ADRL pseudo-instruction Load a PC-relative address into a register 16.12 ADRL pseudo-instruction
ADRP Form PC-relative address to 4KB page 16.13 ADRP
AND (immediate) Bitwise AND (immediate) 16.14 AND (immediate)
AND (shifted register) Bitwise AND (shifted register) 16.15 AND (shifted register)
ANDS (immediate) Bitwise AND (immediate), setting flags 16.16 ANDS (immediate)
ANDS (shifted register) Bitwise AND (shifted register), setting flags 16.17 ANDS (shifted register)
ASR (register) Arithmetic Shift Right (register) 16.18 ASR (register)
ASR (immediate) Arithmetic Shift Right (immediate) 16.19 ASR (immediate)
ASRV Arithmetic Shift Right Variable 16.20 ASRV
AT Address Translate 16.21 AT
B. Branch conditionally 16.22 B.
B Branch 16.23 B
BFI Bitfield Insert 16.24 BFI
BFM Bitfield Move 16.25 BFM
BFXIL Bitfield extract and insert at low end 16.26 BFXIL
BIC (shifted register) Bitwise Bit Clear (shifted register) 16.27 BIC (shifted register)
BICS (shifted register) Bitwise Bit Clear (shifted register), setting flags 16.28 BICS (shifted register)
BL Branch with Link 16.29 BL
BLR Branch with Link to Register 16.30 BLR
BR Branch to Register 16.31 BR
BRK Breakpoint instruction 16.32 BRK
CBNZ Compare and Branch on Nonzero 16.33 CBNZ
CBZ Compare and Branch on Zero 16.34 CBZ
CCMN (immediate) Conditional Compare Negative (immediate) 16.35 CCMN (immediate)
CCMN (register) Conditional Compare Negative (register) 16.36 CCMN (register)
CCMP (immediate) Conditional Compare (immediate) 16.37 CCMP (immediate)
CCMP (register) Conditional Compare (register) 16.38 CCMP (register)
CINC Conditional Increment 16.39 CINC
CINV Conditional Invert 16.40 CINV
CLREX Clear Exclusive 16.41 CLREX
CLS Count leading sign bits 16.42 CLS
CLZ Count leading zero bits 16.43 CLZ
CMN (extended register) Compare Negative (extended register) 16.44 CMN (extended register)
CMN (immediate) Compare Negative (immediate) 16.45 CMN (immediate)
CMN (shifted register) Compare Negative (shifted register) 16.46 CMN (shifted register)
CMP (extended register) Compare (extended register) 16.47 CMP (extended register)
CMP (immediate) Compare (immediate) 16.48 CMP (immediate)
CMP (shifted register) Compare (shifted register) 16.49 CMP (shifted register)
CNEG Conditional Negate 16.50 CNEG
CRC32B, CRC32H, CRC32W, CRC32X CRC32 checksum 16.51 CRC32B, CRC32H, CRC32W, CRC32X
CRC32CB, CRC32CH, CRC32CW, CRC32CX CRC32C checksum 16.52 CRC32CB, CRC32CH, CRC32CW, CRC32CX
CSEL Conditional Select 16.53 CSEL
CSET Conditional Set 16.54 CSET
CSETM Conditional Set Mask 16.55 CSETM
CSINC Conditional Select Increment 16.56 CSINC
CSINV Conditional Select Invert 16.57 CSINV
CSNEG Conditional Select Negation 16.58 CSNEG
DC Data Cache operation 16.59 DC
DCPS1 Debug Change PE State to EL1 16.60 DCPS1
DCPS2 Debug Change PE State to EL2 16.61 DCPS2
DCPS3 Debug Change PE State to EL3 16.62 DCPS3
DMB Data Memory Barrier 16.63 DMB
DRPS Debug restore process state 16.64 DRPS
DSB Data Synchronization Barrier 16.65 DSB
EON (shifted register) Bitwise Exclusive OR NOT (shifted register) 16.66 EON (shifted register)
EOR (immediate) Bitwise Exclusive OR (immediate) 16.67 EOR (immediate)
EOR (shifted register) Bitwise Exclusive OR (shifted register) 16.68 EOR (shifted register)
ERET Returns from an exception 16.69 ERET
EXTR Extract register 16.70 EXTR
HINT Hint instruction 16.71 HINT
HLT Halt instruction 16.72 HLT
HVC Hypervisor call to allow OS code to call the Hypervisor 16.73 HVC
IC Instruction Cache operation 16.74 IC
ISB Instruction Synchronization Barrier 16.75 ISB
LSL (register) Logical Shift Left (register) 16.76 LSL (register)
LSL (immediate) Logical Shift Left (immediate) 16.77 LSL (immediate)
LSLV Logical Shift Left Variable 16.78 LSLV
LSR (register) Logical Shift Right (register) 16.79 LSR (register)
LSR (immediate) Logical Shift Right (immediate) 16.80 LSR (immediate)
LSRV Logical Shift Right Variable 16.81 LSRV
MADD Multiply-Add 16.82 MADD
MNEG Multiply-Negate 16.83 MNEG
MOV (to or from SP) Move between register and stack pointer 16.84 MOV (to or from SP)
MOV (inverted wide immediate) Move (inverted wide immediate) 16.85 MOV (inverted wide immediate)
MOV (wide immediate) Move (wide immediate) 16.86 MOV (wide immediate)
MOV (bitmask immediate) Move (bitmask immediate) 16.87 MOV (bitmask immediate)
MOV (register) Move (register) 16.88 MOV (register)
MOVK Move wide with keep 16.89 MOVK
MOVL pseudo-instruction Load a register with either a 32-bit or 64-bit immediate value or any address 16.90 MOVL pseudo-instruction
MOVN Move wide with NOT 16.91 MOVN
MOVZ Move wide with zero 16.92 MOVZ
MRS Move System Register 16.93 MRS
MSR (immediate) Move immediate value to Special Register 16.94 MSR (immediate)
MSR (register) Move general-purpose register to System Register 16.95 MSR (register)
MSUB Multiply-Subtract 16.96 MSUB
MUL Multiply 16.97 MUL
MVN Bitwise NOT 16.98 MVN
NEG (shifted register) Negate (shifted register) 16.99 NEG (shifted register)
NEGS Negate, setting flags 16.100 NEGS
NGC Negate with Carry 16.101 NGC
NGCS Negate with Carry, setting flags 16.102 NGCS
NOP No Operation 16.103 NOP
ORN (shifted register) Bitwise OR NOT (shifted register) 16.104 ORN (shifted register)
ORR (immediate) Bitwise OR (immediate) 16.105 ORR (immediate)
ORR (shifted register) Bitwise OR (shifted register) 16.106 ORR (shifted register)
RBIT Reverse bit order 16.107 RBIT
RET Return from subroutine 16.108 RET
REV16 Reverse bytes in 16-bit halfwords 16.109 REV16
REV32 Reverse bytes in 32-bit words 16.110 REV32
REV Reverse Bytes 16.111 REV
ROR (immediate) Rotate right (immediate) 16.112 ROR (immediate)
ROR (register) Rotate Right (register) 16.113 ROR (register)
RORV Rotate Right Variable 16.114 RORV
SBC Subtract with Carry 16.115 SBC
SBCS Subtract with Carry, setting flags 16.116 SBCS
SBFIZ Signed Bitfield Insert in Zero 16.117 SBFIZ
SBFM Signed Bitfield Move 16.118 SBFM
SBFX Signed Bitfield Extract 16.119 SBFX
SDIV Signed Divide 16.120 SDIV
SEV Send Event 16.121 SEV
SEVL Send Event Local 16.122 SEVL
SMADDL Signed Multiply-Add Long 16.123 SMADDL
SMC Supervisor call to allow OS or Hypervisor code to call the Secure Monitor 16.124 SMC
SMNEGL Signed Multiply-Negate Long 16.125 SMNEGL
SMSUBL Signed Multiply-Subtract Long 16.126 SMSUBL
SMULH Signed Multiply High 16.127 SMULH
SMULL Signed Multiply Long 16.128 SMULL
SUB (extended register) Subtract (extended register) 16.129 SUB (extended register)
SUB (immediate) Subtract (immediate) 16.130 SUB (immediate)
SUB (shifted register) Subtract (shifted register) 16.131 SUB (shifted register)
SUBS (extended register) Subtract (extended register), setting flags 16.132 SUBS (extended register)
SUBS (immediate) Subtract (immediate), setting flags 16.133 SUBS (immediate)
SUBS (shifted register) Subtract (shifted register), setting flags 16.134 SUBS (shifted register)
SVC Supervisor call to allow application code to call the OS 16.135 SVC
SXTB Signed Extend Byte 16.136 SXTB
SXTH Sign Extend Halfword 16.137 SXTH
SXTW Sign Extend Word 16.138 SXTW
SYS System instruction 16.139 SYS
SYSL System instruction with result 16.140 SYSL
TBNZ Test bit and Branch if Nonzero 16.141 TBNZ
TBZ Test bit and Branch if Zero 16.142 TBZ
TLBI TLB Invalidate operation 16.143 TLBI
TST (immediate) Test bits (immediate), setting the condition flags and discarding the result 16.144 TST (immediate)
TST (shifted register) Test (shifted register) 16.145 TST (shifted register)
UBFIZ Unsigned Bitfield Insert in Zero 16.146 UBFIZ
UBFM Unsigned Bitfield Move 16.147 UBFM
UBFX Unsigned Bitfield Extract 16.148 UBFX
UDIV Unsigned Divide 16.149 UDIV
UMADDL Unsigned Multiply-Add Long 16.150 UMADDL
UMNEGL Unsigned Multiply-Negate Long 16.151 UMNEGL
UMSUBL Unsigned Multiply-Subtract Long 16.152 UMSUBL
UMULH Unsigned Multiply High 16.153 UMULH
UMULL Unsigned Multiply Long 16.154 UMULL
UXTB Unsigned Extend Byte 16.155 UXTB
UXTH Unsigned Extend Halfword 16.156 UXTH
WFE Wait For Event 16.157 WFE
WFI Wait For Interrupt 16.158 WFI