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ST1 (vector, multiple structures)

Store multiple 1-element structures from one, two three or four registers.

Syntax

ST1 { Vt.T }, [Xn|SP], imm ; T1 One register, immediate offset-T32, Post-index

ST1 { Vt.T }, [Xn|SP], Xm ; T1 One register, register offset-T32, Post-index

ST1 { Vt.T, Vt2.T }, [Xn|SP], imm ; T1 Two registers, immediate offset-T32, Post-index

ST1 { Vt.T, Vt2.T }, [Xn|SP], Xm ; T1 Two registers, register offset-T32, Post-index

ST1 { Vt.T, Vt2.T, Vt3.T }, [Xn|SP], imm ; T1 Three registers, immediate offset-T32, Post-index

ST1 { Vt.T, Vt2.T, Vt3.T }, [Xn|SP], Xm ; T1 Three registers, register offset-T32, Post-index

ST1 { Vt.T, Vt2.T, Vt3.T, Vt4.T }, [Xn|SP], imm ; T1 Four registers, immediate offset-T32, Post-index

ST1 { Vt.T, Vt2.T, Vt3.T, Vt4.T }, [Xn|SP], Xm ; T1 Four registers, register offset-T32, Post-index

Where:

Vt2

Is the name of the second SIMD and FP register to be transferred.

Vt3

Is the name of the third SIMD and FP register to be transferred.

Vt4

Is the name of the fourth SIMD and FP register to be transferred.

imm

Is the post-index immediate offset:

One register, immediate offset

Can be one of #8 or #16.

Two registers, immediate offset

Can be one of #16 or #32.

Three registers, immediate offset

Can be one of #24 or #48.

Four registers, immediate offset

Can be one of #32 or #64.

Xm

Is the 64-bit name of the general-purpose post-index register, excluding XZR.

Vt

Is the name of the first or only SIMD and FP register to be transferred.

T

Is an arrangement specifier, and can be one of the values shown in Usage.

Xn|SP

Is the 64-bit name of the general-purpose base register or stack pointer.

Usage

The following table shows valid specifier combinations:

Table 20-81 ST1 (One register, immediate offset-T32) specifier combinations

T imm
8B #8
16B #16
4H #8
8H #16
2S #8
4S #16
1D #8
2D #16

Table 20-82 ST1 (Two registers, immediate offset-T32) specifier combinations

T imm
8B #16
16B #32
4H #16
8H #32
2S #16
4S #32
1D #16
2D #32

Table 20-83 ST1 (Three registers, immediate offset-T32) specifier combinations

T imm
8B #24
16B #48
4H #24
8H #48
2S #24
4S #48
1D #24
2D #48

Table 20-84 ST1 (Four registers, immediate offset-T32) specifier combinations

T imm
8B #32
16B #64
4H #32
8H #64
2S #32
4S #64
1D #32
2D #64
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