VLDn (single n-element structure to all lanes)
Vector Load single n
-element structure to all lanes.
Syntax
VLD
{n
}.cond
datatype
,
[list
{@Rn
}]{!} align
VLD
{n
}.cond
datatype
,
[list
{@Rn
}],
align
Rm
where:
n
must be one of 1, 2, 3, or 4.
cond
is an optional condition code.
datatype
see the following table.
list
-
is the list of Advanced SIMD registers enclosed in braces, { and }. See the following table for options.
Rn
is the ARM register containing the base address.
cannot be PC.Rn
align
specifies an optional alignment. See the following table for options.
!
if ! is present,
is updated to (Rn
+ the number of bytes transferred by the instruction). The update occurs after all the loads have taken place.Rn
Rm
is an ARM register containing an offset from the base address. If
is present, the instruction updatesRm
to (Rn
+Rn
) after using the address to access memory.Rm
cannot be SP or PC.Rm
Operation
VLD
loads multiple copies of one n
n
-element structure from memory into one or more Advanced SIMD registers.
Table 14-5 Permitted combinations of parameters for VLDn (single n-element structure to all lanes)
n |
datatype |
list a | align
b |
alignment |
---|---|---|---|---|
1 | 8 |
{Dd[]} |
- | Standard only |
{Dd[],D(d+1)[]} |
- | Standard only | ||
16 |
{Dd[]} |
@16 |
2-byte | |
{Dd[],D(d+1)[]} |
@16 |
2-byte | ||
32 |
{Dd[]} |
@32 |
4-byte | |
{Dd[],D(d+1)[]} |
@32 |
4-byte | ||
2 | 8 |
{Dd[], D(d+1)[]} |
@8 |
byte |
{Dd[], D(d+2)[]} |
@8 |
byte | ||
16 |
{Dd[], D(d+1)[]} |
@16 |
2-byte | |
{Dd[], D(d+2)[]} |
@16 |
2-byte | ||
32 |
{Dd[], D(d+1)[]} |
@32 |
4-byte | |
{Dd[], D(d+2)[]} |
@32 |
4-byte | ||
3 | 8 , 16 , or 32 |
{Dd[], D(d+1)[], D(d+2)[]} |
- | Standard only |
{Dd[], D(d+2)[], D(d+4)[]} |
- | Standard only | ||
4 | 8 |
{Dd[], D(d+1)[], D(d+2)[], D(d+3)[]} |
@32 |
4-byte |
{Dd[], D(d+2)[], D(d+4)[], D(d+6)[]} |
@32 |
4-byte | ||
16 |
{Dd[], D(d+1)[], D(d+2)[], D(d+3)[]} |
@64 |
8-byte | |
{Dd[], D(d+2)[], D(d+4)[], D(d+6)[]} |
@64 |
8-byte | ||
32 |
{Dd[], D(d+1)[], D(d+2)[], D(d+3)[]} |
@64 or @128 |
8-byte or 16-byte | |
{Dd[], D(d+2)[], D(d+4)[], D(d+6)[]} |
@64 or @128 |
8-byte or 16-byte |
Related reference
Every register in the list must be in the range D0
-D31
.
can be omitted. In this case, standard alignment rules
apply.align