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ARM Compiler armasm User Guide : LDC and LDC2

LDC and LDC2

Transfer Data from memory to Coprocessor.

Note

LDC2 is not supported in ARMv8.

Syntax

op{L}{cond} coproc, CRd, [Rn]

op{L}{cond} coproc, CRd, [Rn, #{-}offset] ; offset addressing

op{L}{cond} coproc, CRd, [Rn, #{-}offset]! ; pre-index addressing

op{L}{cond} coproc, CRd, [Rn], #{-}offset ; post-index addressing

op{L}{cond} coproc, CRd, label

op{L}{cond} coproc, CRd, [Rn], {option}

where:

op
is LDC or LDC2.
cond

is an optional condition code.

In A32 code, cond is not permitted for LDC2.

L
is an optional suffix specifying a long transfer.
coproc

is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer whose value must be:

  • In the range 0 to 15 in ARMv7 and earlier.
  • 14 in ARMv8.
CRd
is the coprocessor register to load.
Rn
is the register on which the memory address is based. If PC is specified, the value used is the address of the current instruction plus eight.
-
is an optional minus sign. If - is present, the offset is subtracted from Rn. Otherwise, the offset is added to Rn.
offset
is an expression evaluating to a multiple of 4, in the range 0 to 1020.
!
is an optional suffix. If ! is present, the address including the offset is written back into Rn.
label

is a word-aligned PC-relative expression.

label must be within 1020 bytes of the current instruction.

option
is a coprocessor option in the range 0-255, enclosed in braces.

Usage

The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.

Architectures

These 32-bit instructions are available in A32 and T32.

There are no 16-bit versions of these instructions in T32.

Register restrictions

You cannot use PC for Rn in the pre-index and post-index instructions. These are the forms that write back to Rn.

Related reference

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