You copied the Doc URL to your clipboard.

ARM Compiler armasm User Guide : MVN

MVN

Move Not.

Syntax

MVN{S}{cond} Rd, Operand2

where:

S
is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.
cond
is an optional condition code.
Rd
is the destination register.
Operand2
is a flexible second operand.

Operation

The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and places the result into Rd.

In certain circumstances, the assembler can substitute MVN for MOV, or MOV for MVN. Be aware of this when reading disassembly listings.

Use of PC and SP in 32-bit T32 MVN

You cannot use PC (R15) for Rd, or in Operand2, in 32-bit T32 MVN instructions. You cannot use SP (R13) for Rd, or in Operand2.

Use of PC and SP in 16-bit T32 instructions

You cannot use PC or SP in any MVN{S} 16-bit T32 instructions.

Use of PC and SP in A32 MVN

You cannot use PC for Rd or any operand in any data processing instruction that has a register-controlled shift.

In instructions without register-controlled shift, use of PC is deprecated.

You can use SP for Rd or Rm, but this is deprecated.

Note

  • PC and SP in A32 instructions are deprecated.

If you use PC as Rm, the value used is the address of the instruction plus 8.

If you use PC as Rd:

  • Execution branches to the address corresponding to the result.
  • If you use the S suffix, see the SUBS pc,lr instruction.

Condition flags

If S is specified, the instruction:

  • Updates the N and Z flags according to the result.
  • Can update the C flag during the calculation of Operand2.
  • Does not affect the V flag.

16-bit instructions

The following forms of this instruction are available in T32 code, and are 16-bit instructions:

MVNS Rd, Rm
Rd and Rm must both be Lo registers. This form can only be used outside an IT block.
MVN{cond} Rd, Rm
Rd and Rm must both be Lo registers. This form can only be used inside an IT block.

Architectures

This instruction is available in A32 and T32.

Correct example

    MVNNE   r11, #0xF000000B ; A32 only. This immediate value is not
                             ; available in T32.

Incorrect example

    MVN     pc,r3,ASR r0     ; PC not permitted with 
                             ; register-controlled shift
Was this page helpful? Yes No