Dual 16-bit Signed Multiply with Subtraction of products and 32-bit accumulation.
is an optional condition code.
is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.
is the destination register.
are the registers holding the operands.
is the register holding the accumulate operand.
SMLSD multiplies the bottom halfword of
Rn with the bottom
Rm, and the top halfword of
Rn with the
top halfword of
Rm. It then subtracts the second product from the first,
adds the difference to the value in
Ra, and stores the result to
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
This instruction does not change the flags.
The 32-bit instruction is available in A32 and T32.
For the ARMv7-M architecture, the 32-bit T32 instruction is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in T32.
SMLSD r1, r2, r0, r7 SMLSDX r11, r10, r2, r3