Parallel halfword Saturate.
is an optional condition code.
is the destination register.
specifies the bit position to saturate to, in the range 1 to 16.
is the register holding the operand.
Halfword-wise signed saturation to any bit position.
SSAT16 instruction saturates
each signed halfword to the signed range –2sat–1 ≤
x ≤ 2sat–1 –1.
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
If saturation occurs on either halfword, this instruction
sets the Q flag. To read the state of the Q flag, use an
The 32-bit instruction is available in A32 and T32.
For the ARMv7-M architecture, the 32-bit T32 instruction is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in T32.
SSAT16 r7, #12, r7
SSAT16 r1, #16, r2, LSL #4 ; shifts not permitted with halfword ; saturations