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ARM Compiler armasm User Guide : STLEX

STLEX

Store-Release Register Exclusive.

Note

This instruction is supported only in ARMv8.

Syntax

STLEX{cond} Rd, Rt, [Rn]

STLEXB{cond} Rd, Rt, [Rn]

STLEXH{cond} Rd, Rt, [Rn]

STLEXD{cond} Rd, Rt, Rt2, [Rn]

where:

cond
is an optional condition code.
Rd
is the destination register for the returned status.
Rt
is the register to load or store.
Rt2
is the second register for doubleword loads or stores.
Rn
is the register on which the memory address is based.

Operation

STLEX performs a conditional store to memory. The conditions are as follows:

  • If the physical address does not have the Shared TLB attribute, and the executing processor has an outstanding tagged physical address, the store takes place, the tag is cleared, and the value 0 is returned in Rd.
  • If the physical address does not have the Shared TLB attribute, and the executing processor does not have an outstanding tagged physical address, the store does not take place, and the value 1 is returned in Rd.
  • If the physical address has the Shared TLB attribute, and the physical address is tagged as exclusive access for the executing processor, the store takes place, the tag is cleared, and the value 0 is returned in Rd.
  • If the physical address has the Shared TLB attribute, and the physical address is not tagged as exclusive access for the executing processor, the store does not take place, and the value 1 is returned in Rd.

If any loads or stores appear before STLEX in program order, then all observers are guaranteed to observe the loads and stores before observing the store-release. Loads and stores appearing after STLEX are unaffected.

All store-release operations are multi-copy atomic.

Restrictions

The PC must not be used for any of Rd, Rt, Rt2, or Rn.

For STLEX, Rd must not be the same register as Rt, Rt2, or Rn.

For A32 instructions:

  • SP can be used but use of SP for any of Rd, Rt, or Rt2 is deprecated.
  • For STLEXD, Rt must be an even numbered register, and not LR.
  • Rt2 must be R(t+1).

For T32 instructions, SP can be used for Rn, but must not be used for any of Rd, Rt, or Rt2.

Usage

Use LDAEX and STLEX to implement interprocess communication in multiple-processor and shared-memory systems.

For reasons of performance, keep the number of instructions between corresponding LDAEX and STLEX instructions to a minimum.

Note

The address used in a STLEX instruction must be the same as the address in the most recently executed LDAEX instruction.

Availability

These 32-bit instructions are available in A32 and T32.

There are no 16-bit versions of these instructions.

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