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ARM Compiler armasm User Guide : SXTH

SXTH

Sign extend Halfword.

Syntax

SXTH{cond} {Rd}, Rm {,rotation}

where:

cond

is an optional condition code.

Rd

is the destination register.

Rm

is the register holding the value to extend.

rotation

is one of:

ROR #8

Value from Rm is rotated right 8 bits.

ROR #16

Value from Rm is rotated right 16 bits.

ROR #24

Value from Rm is rotated right 24 bits.

If rotation is omitted, no rotation is performed.

Operation

SXTH extends a 16-bit value to a 32-bit value. It does this by:

  1. Rotating the value from Rm right by 0, 8, 16 or 24 bits.

  2. Extracting bits[15:0] from the value obtained.

  3. Sign extending to 32 bits.

Register restrictions

You cannot use PC for any operand.

You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.

Condition flags

This instruction does not change the flags.

16-bit instructions

The following form of this instruction is available in T32 code, and is a 16-bit instruction:

SXTH Rd, Rm

Rd and Rm must both be Lo registers.

Availability

The 32-bit instruction is available in A32 and T32.

For the ARMv7-M architecture, the 32-bit T32 instruction is only available in an ARMv7E-M implementation.

The 16-bit instruction is available in T32.

Example

    SXTH         r3, r9, r4

Incorrect example

    SXTH     r9, r3, r2, ROR #12 ; rotation must be by 0, 8, 16, or 24.

Related reference

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