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ARM Compiler armasm User Guide : LDRSH (register)

LDRSH (register)

Load Register Signed Halfword (register).

Syntax

LDRSH Wt, [Xn|SP, Rm{, extend {amount}}] ; 32-bit general registers

LDRSH Xt, [Xn|SP, Rm{, extend {amount}}] ; 64-bit general registers

Where:

Wt

Is the 32-bit name of the general-purpose register to be transferred.

Xt

Is the 64-bit name of the general-purpose register to be transferred.

Xn|SP

Is the 64-bit name of the general-purpose base register or stack pointer.

R

Is the index width specifier, and can be either W or X.

m

Is the number [0-30] of the general-purpose index register or the name ZR (31).

extend

Is the index extend/shift specifier, defaulting to LSL, and can be one of the values shown in Usage.

amount

Is the index shift amount, optional and defaulting to #0 when extend is not LSL, and can be either #0 or #1.

Usage

Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it, and writes it to a register. For information about memory accesses see Load/Store addressing modes in the ARMv8-A Architecture Reference Manual.

The following table shows the valid specifier combinations:

Table 17-7 LDRSH (register) specifier combinations

R extend
W SXTW
W UXTW
X LSL
X SXTX
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