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ARM Compiler armasm User Guide : ADD (extended register)

ADD (extended register)

Add (extended register).

Syntax

ADD Wd|WSP, Wn|WSP, Wm{, extend {#amount}} ; 32-bit general registers

ADD Xd|SP, Xn|SP, Rm{, extend {#amount}} ; 64-bit general registers

Where:

Wd|WSP

Is the 32-bit name of the destination general-purpose register or stack pointer.

Wn|WSP

Is the 32-bit name of the first source general-purpose register or stack pointer.

Wm

Is the 32-bit name of the second general-purpose source register.

extend

Is the extension to be applied to the second source operand:

32-bit general registers

Can be one of UXTB, UXTH, LSL|UXTW, UXTX, SXTB, SXTH, SXTW or SXTX.

If Rd or Rn is WSP then LSL is preferred rather than UXTW, and can be omitted when amount is 0. In all other cases extend is required and must be UXTW rather than LSL.

64-bit general registers

Can be one of UXTB, UXTH, UXTW, LSL|UXTX, SXTB, SXTH, SXTW or SXTX.

If Rd or Rn is SP then LSL is preferred rather than UXTX, and can be omitted when amount is 0. In all other cases extend is required and must be UXTX rather than LSL.

Xd|SP

Is the 64-bit name of the destination general-purpose register or stack pointer.

Xn|SP

Is the 64-bit name of the first source general-purpose register or stack pointer.

R

Is a width specifier, and can be either W or X.

m

Is the number [0-30] of the second general-purpose source register or the name ZR (31).

amount

Is the left shift amount to be applied after extension in the range 0 to 4, defaulting to 0. It must be absent when extend is absent, is required when extend is LSL, and is optional when extend is present but not LSL.

Operation

Add (extended register) adds a register value and a sign or zero-extended register value, followed by an optional left shift amount, and writes the result to the destination register. The argument that is extended from the Rm register can be a byte, halfword, word, or doubleword.

Rd = Rn + LSL(extend(Rm), amount), where R is either W or X.

Usage

The following table shows the valid specifier combinations:

Table 16-2 ADD (64-bit general registers) specifier combinations

R extend
W SXTB
W SXTH
W SXTW
W UXTB
W UXTH
W UXTW
X LSL|UXTX
X SXTX
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