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ARM Compiler armasm User Guide : LD1R (vector)

LD1R (vector)

Load single 1-element structure and replicate to all lanes (of one register).

Syntax

LD1R { Vt.T }, [Xn|SP] ; No offset

LD1R { Vt.T }, [Xn|SP], imm ; Immediate offset, Post-index

LD1R { Vt.T }, [Xn|SP], Xm ; Register offset, Post-index

Where:

imm

Is the post-index immediate offset, and can be one of the values shown in Usage.

Xm

Is the 64-bit name of the general-purpose post-index register, excluding XZR.

Vt

Is the name of the first or only SIMD and FP register to be transferred.

T

Is an arrangement specifier, and can be one of the values shown in Usage.

Xn|SP

Is the 64-bit name of the general-purpose base register or stack pointer.

Usage

The following table shows the valid specifier combinations:

Table 20-22 LD1R (Immediate offset) specifier combinations

T imm
8B #1
16B #1
4H #2
8H #2
2S #4
4S #4
1D #8
2D #8
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