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ARM Compiler armasm User Guide : LD3R (vector)

LD3R (vector)

Load single 3-element structure and replicate to all lanes of three registers.

Syntax

LD3R { Vt.T, Vt2.T, Vt3.T }, [Xn|SP] ; No offset

LD3R { Vt.T, Vt2.T, Vt3.T }, [Xn|SP], imm ; Immediate offset, Post-index

LD3R { Vt.T, Vt2.T, Vt3.T }, [Xn|SP], Xm ; Register offset, Post-index

Where:

Vt

Is the name of the first or only SIMD and FP register to be transferred.

Vt2

Is the name of the second SIMD and FP register to be transferred.

Vt3

Is the name of the third SIMD and FP register to be transferred.

imm

Is the post-index immediate offset, and can be one of the values shown in Usage.

Xm

Is the 64-bit name of the general-purpose post-index register, excluding XZR.

T

Is an arrangement specifier, and can be one of the values shown in Usage.

Xn|SP

Is the 64-bit name of the general-purpose base register or stack pointer.

Usage

The following table shows the valid specifier combinations:

Table 20-24 LD3R (Immediate offset) specifier combinations

T imm
8B #3
16B #3
4H #6
8H #6
2S #12
4S #12
1D #24
2D #24
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