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Summary of Advanced SIMD instructions
Most Advanced SIMD instructions are not available in floating-point.
The following table shows a summary of Advanced SIMD instructions that are not available as floating-point instructions:
Table 14-1 Summary of Advanced SIMD instructions
Mnemonic | Brief description |
---|---|
VABA , VABD |
Absolute difference and Accumulate, Absolute Difference |
VABS |
Absolute value |
VACGE , VACGT |
Absolute Compare Greater than or Equal, Greater Than |
VACLE , VACLT |
Absolute Compare Less than or Equal, Less Than (pseudo-instructions) |
VADD |
Add |
VADDHN |
Add, select High half |
VAND |
Bitwise AND |
VAND |
Bitwise AND (pseudo-instruction) |
VBIC |
Bitwise Bit Clear (register) |
VBIC |
Bitwise Bit Clear (immediate) |
VBIF , VBIT , VBSL |
Bitwise Insert if False, Insert if True, Select |
VCEQ , VCLE , VCLT |
Compare Equal, Less than or Equal, Compare Less Than |
VCGE , VCGT |
Compare Greater than or Equal, Greater Than |
VCLE , VCLT |
Compare Less than or Equal, Compare Less Than (pseudo-instruction) |
VCLS , VCLZ , VCNT |
Count Leading Sign bits, Count Leading Zeros, and Count set bits |
VCVT |
Convert fixed-point or integer to floating-point, floating-point to integer or fixed-point |
VCVT |
Convert floating-point to integer with directed rounding modes |
VCVT |
Convert between half-precision and single-precision floating-point numbers |
VDUP |
Duplicate scalar to all lanes of vector |
VEOR |
Bitwise Exclusive OR |
VEXT |
Extract |
VFMA , VFMS |
Fused Multiply Accumulate, Fused Multiply Subtract |
VHADD , VHSUB |
Halving Add, Halving Subtract |
VLD |
Vector Load |
VMAX , VMIN |
Maximum, Minimum |
VMAXNM , VMINNM |
Maximum, Minimum, consistent with IEEE 754-2008 |
VMLA , VMLS |
Multiply Accumulate, Multiply Subtract (vector) |
VMLA , VMLS |
Multiply Accumulate, Multiply Subtract (by scalar) |
VMOV |
Move (immediate) |
VMOV |
Move (register) |
VMOVL , VMOV{U}N |
Move Long, Move Narrow (register) |
VMUL |
Multiply (vector) |
VMUL |
Multiply (by scalar) |
VMVN |
Move Negative (immediate) |
VNEG |
Negate |
VORN |
Bitwise OR NOT |
VORN |
Bitwise OR NOT (pseudo-instruction) |
VORR |
Bitwise OR (register) |
VORR |
Bitwise OR (immediate) |
VPADD , VPADAL |
Pairwise Add, Pairwise Add and Accumulate |
VPMAX , VPMIN |
Pairwise Maximum, Pairwise Minimum |
VQABS |
Absolute value, saturate |
VQADD |
Add, saturate |
VQDMLAL , VQDMLSL |
Saturating Doubling Multiply Accumulate, and Multiply Subtract |
VQDMULL |
Saturating Doubling Multiply |
VQDMULH |
Saturating Doubling Multiply returning High half |
VQMOV{U}N |
Saturating Move (register) |
VQNEG |
Negate, saturate |
VQRDMULH |
Saturating Doubling Multiply returning High half |
VQRSHL |
Shift Left, Round, saturate (by signed variable) |
VQRSHR{U}N |
Shift Right, Round, saturate (by immediate) |
VQSHL |
Shift Left, saturate (by immediate) |
VQSHL |
Shift Left, saturate (by signed variable) |
VQSHR{U}N |
Shift Right, saturate (by immediate) |
VQSUB |
Subtract, saturate |
VRADDHN |
Add, select High half, Round |
VRECPE |
Reciprocal Estimate |
VRECPS |
Reciprocal Step |
VREV |
Reverse elements |
VRHADD |
Halving Add, Round |
VRINT |
Round to integer |
VRSHR |
Shift Right and Round (by immediate) |
VRSHRN |
Shift Right, Round, Narrow (by immediate) |
VRSQRTE |
Reciprocal Square Root Estimate |
VRSQRTS |
Reciprocal Square Root Step |
VRSRA |
Shift Right, Round, and Accumulate (by immediate) |
VRSUBHN |
Subtract, select High half, Round |
VSHL |
Shift Left (by immediate) |
VSHR |
Shift Right (by immediate) |
VSHRN |
Shift Right, Narrow (by immediate) |
VSLI |
Shift Left and Insert |
VSRA |
Shift Right, Accumulate (by immediate) |
VSRI |
Shift Right and Insert |
VST |
Vector Store |
VSUB |
Subtract |
VSUBHN |
Subtract, select High half |
VSWP |
Swap vectors |
VTBL , VTBX |
Vector table look-up |
VTRN |
Vector transpose |
VTST |
Test bits |
VUZP , VZIP |
Vector interleave and de-interleave |